1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a stacked memory device suitable for performing a refresh operation.
2. Description of the Related Art
In general, volatile memory devices, such as DRAM or DDR SDRAM perform a refresh operation periodically to prevent data stored in a memory cell from being lost.
The refresh operation may be performed in an auto-refresh mode or a self-refresh mode. In the auto-refresh mode, a memory device performs a refresh operation in response to a refresh command applied from an external source during a normal operation of the memory device. In the self-refresh mode, the memory device performs a refresh operation in response to a refresh command signal that is internally generated, while the memory device is not operated (e.g., in a power-down mode).
When the refresh characteristics of a few cells are deteriorated even though the overall refresh characteristic of DRAM is not affected by the deterioration, the overall refresh performance may be degraded by the few cells. Various methods have been proposed for refreshing one or more cells having a shorter data retention time than the refresh cycle tREF based on the design specification of the DRAM. Such cells are referred to hereinafter as weak cells.
A two-dimensional (2D) structure, in which a plurality of semiconductor chips having integrated circuits are disposed on a printed circuit board (PCB) using wires or bumps, has been used as a conventional packaging technology. With the rapid development of the semiconductor memory technology, the packaging technology for semiconductor integrated devices has required high integration and high performance. Thus, a variety of technologies have been developed for obtaining a three-dimensional (3D) structure, in which a plurality of semiconductor chips are vertically stacked.
In a stacked memory device having a three-dimensional structure, a plurality of memory chips may be vertically stacked. The semiconductor chips stacked in the vertical direction are mounted on a substrate for a semiconductor package, and the semiconductor chips may be coupled electrically to each other through a plurality of through-chip vias, for example, through-silicon vias (TSVs).
Such stacked memory devices also require a method for refreshing weak cells.